# Project 1

• Read Chapter 1 and Appendix A.

• Create a repository on Bitbucket named exactly csci201-project-01. Invite me (joshuaeckroth) as a reader.

Implement the following logic gates by writing an HDL file for each. Start with the HDL templates provided. Be sure to test your implementations with the corresponding test scripts.

You may only use the builtin Nand gate and any other gates you correctly implement during this project.

## Gates to implement

Download a ZIP file containing all of the above, including files for gates that I am not asking you to implement.

A gate is considered correct if it passes all of the tests defined in its corresponding .tst script and .cmp comparison output.

• All gates correct: 5 pts
• At least 10 gates correct: 4 pts
• At least 8 gates correct: 3 pts
• At least 6 gates correct: 2 pts
• At least 2 gates correct: 1 pts
• 0 gates correct: 0 pts

## Extra credit

If you implement your gates with the fewest low-level gates possible (fewest “PARTS” in the HDL file), you receive extra credit.

• All gates are as simple as possible: +3 pts
• At least 6 gates are as simple as possible: +2 pts
• At least one gate is as simple as possible: +1 pt