Project 2

Implement the following logic gates by writing an HDL file for each. Start with the HDL templates provided. Be sure to test your implementations with the corresponding test scripts.

You may use any gate described in Chapter 1: Nand, Not, And, Or, Xor, Mux, DMux, Not16, And16, Or16, Mux16, Or8Way, Mux4Way16, Mux8Way16, DMux4Way, DMux8Way, plus whatever gates you implement in this project.

Gates to implement

Download a ZIP file containing the necessary files.


A gate is considered correct if it passes all of the tests defined in its corresponding .tst script and .cmp comparison output.

Extra credit

If you implement your gates with the fewest gates possible (fewest “PARTS” in the HDL file), you receive extra credit.

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