Read Chapter 2.
Create a repository on Bitbucket named exactly
csci201-project-02. Invite me (
joshuaeckroth) as a reader.
Implement the following logic gates by writing an HDL file for each. Start with the HDL templates provided. Be sure to test your implementations with the corresponding test scripts.
You may use any gate described in Chapter 1:
DMux8Way, plus whatever gates you implement in this project.
Gates to implement
A gate is considered correct if it passes all of the tests defined in its corresponding
.tst script and
.cmp comparison output.
- All gates correct: 5 pts
ALUcorrect: 3 pts
- All but
ALUcorrect: 2 pts
- No gates correct: 0 pts
If you implement your gates with the fewest gates possible (fewest “PARTS” in the HDL file), you receive extra credit.
ALUas simple as possible: +2 pts
Add16as simple as possible: +1 pt